Pl310 cache controller pdf file download

The addition of an onchip secondary cache, also referred to as a level 2 or l2 cache, is a recognized method of improving the performance of armbased systems when significant memory traffic is generated by the processor. Home documentation ddi0246 a pl310 cache controller technical reference manual glossary pl310 cache controller technical reference manual. Mx 6duallite two master axi bus interfaces output of l2 cache frequency of the core including neon and l1 cache, as per table 8. Primecell level 2 cache controller pl310 technical reference manual. This functionality enables a debugger to download code. This document lists the errata for the arria v sx and st soc devices. In this in this manual the generic term cache controller means the pl310 cache controller. Cache configurability shows how you can use these rtl options to configure the cache controller.

General interrupt controller gic with 128 interrupt support global timer snoop control unit scu 512 kb unified id l2 cache. This functionality enables a debugger to download code or data to. Pl310 technical manual 2114 ram l2 cache verilog code pl310 l2 cache design in verilog amba file write axi verilog code amba axi. Nios ii classic processor reference guide subscribe send feedback nii5v1 2016. View and download tecsun pl310et operation manual online.

Arm architecture reference manual arm v7a and arm v7r arm ddi 0406. This is the arm technical reference manual trm for the pl310 cache controller revision. Read this for a description of the cache controller registers for programming. Pdf pl310 glossary11 glossary12 tcm 2911 trustzone pl310 technical manual. Clken used to drive cache controller inputs in case of integer clock ratio. The freertos bsp for zynq is available for download from the the freertosfreertos website. Download and install the appropriate soceds patch for software version. Mx 6sololite applications processor reference manual. Corelink level 2 mbist controller l2c310 technical reference manual. Arm primecell level 2 mbist controller pl310 technical reference manual. Read this for a description of the cache controller registers for programming details.

Mx 6solo6duallite applications processors data sheet. This is the technical reference manual trm for the pl310 cache controller. Protecting data on smartphones and tablets from memory attacks. Refer to the pl310 cache controller technical reference manual for more information.